Changeset 5c0183 in git for dyn_modules


Ignore:
Timestamp:
Feb 17, 2012, 4:44:11 PM (12 years ago)
Author:
Oleksandr Motsak <motsak@…>
Branches:
(u'spielwiese', 'fe61d9c35bf7c61f2b6cbf1b56e25e2f08d536cc')
Children:
e4f491963f9660b7e75c9817b20efcc8c5fae6fa
Parents:
98c9729eb3e7d8dbe8cbfa1932442589173c8270
git-author:
Oleksandr Motsak <motsak@mathematik.uni-kl.de>2012-02-17 16:44:11+01:00
git-committer:
Oleksandr Motsak <motsak@mathematik.uni-kl.de>2012-02-23 20:35:10+01:00
Message:
fix the induced Schreyer ordering

add: a test due to Chrisian
add: enable detailed debug for the ordering
fix: bugs in induced Schreyer ordering(!?)
fix: the ordering (due to negative offset!)
Location:
dyn_modules/syzextra
Files:
1 added
1 edited

Legend:

Unmodified
Added
Removed
  • dyn_modules/syzextra/mod_main.cc

    r98c972 r5c0183  
    111111  {
    112112    const ring r = (const ring)h->Data();
    113     rWrite(r);
     113    rWrite(r, TRUE);
    114114    PrintLn();
    115115#ifdef RDEBUG
     
    681681  const int posIS = rGetISPos(0, r);
    682682
    683   if( (!isSyz) && (-1 == posIS) )
    684   {
    685     WerrorS("`idPrepare(<...>)` called on incompatible ring (not created by 'MakeSyzCompOrdering' or 'MakeInducedSchreyerOrdering'!)");
    686     return TRUE;
    687   }
    688683
    689684  if ( !( (h!=NULL) && (h->Typ()==MODUL_CMD) && (h->Data() != NULL) ) )
     
    706701  } else
    707702  {
     703      if( (!isSyz) && (-1 == posIS) )
     704      {
     705        WerrorS("`idPrepare(<...>)` called on incompatible ring (not created by 'MakeSyzCompOrdering' or 'MakeInducedSchreyerOrdering'!)");
     706        return TRUE;
     707      }
     708
    708709    if( isSyz )
    709710      iComp = rGetCurrSyzLimit(r);
     
    711712      iComp = id_RankFreeModule(r->typ[posIS].data.is.F, r); // ;
    712713  }
     714 
     715  assume(iComp >= 0);
    713716
    714717
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