Changeset 87ca280 in git

Timestamp:

Jul 5, 2007, 6:14:16 PM (17 years ago)

Author:

Hans Schönemann <hannes@…>

Branches:

(u'spielwiese', 'fe61d9c35bf7c61f2b6cbf1b56e25e2f08d536cc')

Children:

ab47781f09fb7d99efd5ca881281850461a34bbb

Parents:

a87151706a0778c70126d1ae9247ca96165c60ac

Message:

*hannes: again rp


git-svn-id: file:///usr/local/Singular/svn/trunk@10174 2c84dea3-7e68-4137-9b89-c4e89433aadc

File:

• kernel/ring.cc (modified) (6 diffs)

kernel/ring.cc

@@ -2 +2 @@
 *  Computer Algebra System SINGULAR     *
 ****************************************/
-/* $Id: ring.cc,v 1.63 2007-07-05 09:40:41 Singular Exp $ */
+/* $Id: ring.cc,v 1.64 2007-07-05 16:14:16 Singular Exp $ */
 
 /*
@@ -1242 +1242 @@
     // it cannot be both the currRing! :)
     // the currRing is sum!
-    
+
     int l = rVar(R1) + rVar(R2);
     matrix C  = mpNew(l,l);
@@ -2553 +2553 @@
   if ((order[i]== ringorder_ws)
   || (order[i]==ringorder_Ws)
-  || (order[i]== ringorder_wp) 
+  || (order[i]== ringorder_wp)
   || (order[i]==ringorder_Wp)
   || (order[i]== ringorder_a)
@@ -2646 +2646 @@
       r->pFDeg = pTotaldegree;
     }
-    if ((order[0] == ringorder_a) 
-    || (order[0] == ringorder_wp) 
-    || (order[0] == ringorder_Wp) 
-    || (order[0] == ringorder_ws) 
+    if ((order[0] == ringorder_a)
+    || (order[0] == ringorder_wp)
+    || (order[0] == ringorder_Wp)
+    || (order[0] == ringorder_ws)
     || (order[0] == ringorder_Ws))
       r->pFDeg = pWFirstTotalDegree;
@@ -2677 +2677 @@
     r->firstBlockEnds=block1[1];
     r->firstwv = wvhdl[1];
-    if ((order[1] == ringorder_a) 
-    || (order[1] == ringorder_wp) 
-    || (order[1] == ringorder_Wp) 
-    || (order[1] == ringorder_ws) 
+    if ((order[1] == ringorder_a)
+    || (order[1] == ringorder_wp)
+    || (order[1] == ringorder_Wp)
+    || (order[1] == ringorder_ws)
     || (order[1] == ringorder_Ws))
       r->pFDeg = pWFirstTotalDegree;
@@ -2870 +2870 @@
 
       case ringorder_rp:
-        rO_LexVars_neg(j, j_bits, r->block1[i],r->block0[i], prev_ordsgn,
+        rO_LexVars(j, j_bits, r->block1[i],r->block0[i], prev_ordsgn,
                        tmp_ordsgn,v, bits, -1);
         break;